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00043 #include "config.h"
00044
00045
00046
00047 #ifndef NRF_CS_PORT
00048 #error NRF_CS_PORT should be defined somewhere (usually target_board_file.h)
00049 #endif
00050
00051 #ifndef NRF_CS_PIN
00052 #error NRF_CS_PIN should be defined somewhere (usually target_board_file.h)
00053 #endif
00054
00055 #ifndef NRF_CE_PORT
00056 #error NRF_CE_PORT should be defined somewhere (usually target_board_file.h)
00057 #endif
00058
00059 #ifndef NRF_CE_PIN
00060 #error NRF_CE_PIN should be defined somewhere (usually target_board_file.h)
00061 #endif
00062
00063 #ifndef NRF_IRQ_PORT
00064 #error NRF_IRQ_PORT should be defined somewhere (usually target_board_file.h)
00065 #endif
00066
00067 #ifndef NRF_IRQ_PIN
00068 #error NRF_IRQ_PIN should be defined somewhere (usually target_board_file.h)
00069 #endif
00070
00071 #ifndef NRF_port_init
00072 #error NRF_port_init() should be defined somewhere (usually target_board_file.h)
00073 #endif
00074
00075
00076
00077 #define NRF_select() (NRF_CS_PORT &= ~(1<<NRF_CS_PIN))
00078 #define NRF_unselect() (NRF_CS_PORT |= (1<<NRF_CS_PIN))
00079 #define NRF_disable() (NRF_CE_PORT &= ~(1<<NRF_CE_PIN))
00080 #define NRF_enable() (NRF_CE_PORT |= (1<<NRF_CE_PIN))
00081
00082
00083
00084 #define IDLE 0x00 // Idle, no interrupt pending
00085 #define MAX_RT 0x10 // Max #of TX retrans interrupt
00086 #define TX_DS 0x20 // TX data sent interrupt
00087 #define RX_DR 0x40 // RX data received
00088
00089 #define SPI_CFG 0x40 // SPI Configuration register value
00090 #define SPI_CTR 0x01 // SPI Control register values
00091 #define SPI_CLK 0x00 // SYSCLK/2*(SPI_CLK+1) == > 12MHz / 2 = 6MHz
00092 #define SPI0E 0x02 // SPI Enable in XBR0 register
00093
00094
00095
00096 #define READ_REG 0x00 // Define read command to register
00097 #define WRITE_REG 0x20 // Define write command to register
00098 #define RD_RX_PLOAD 0x61 // Define RX payload register address
00099 #define WR_TX_PLOAD 0xA0 // Define TX payload register address
00100 #define FLUSH_TX 0xE1 // Define flush TX register command
00101 #define FLUSH_RX 0xE2 // Define flush RX register command
00102 #define REUSE_TX_PL 0xE3 // Define reuse TX payload register command
00103 #define NOP 0xFF // Define No Operation, might be used to read status register
00104
00105
00106 #define CONFIG 0x00 // 'Config' register address
00107 #define EN_AA 0x01 // 'Enable Auto Acknowledgment' register address
00108 #define EN_RXADDR 0x02 // 'Enabled RX addresses' register address
00109 #define SETUP_AW 0x03 // 'Setup address width' register address
00110 #define SETUP_RETR 0x04 // 'Setup Auto. Retrans' register address
00111 #define RF_CH 0x05 // 'RF channel' register address
00112 #define RF_SETUP 0x06 // 'RF setup' register address
00113 #define STATUS 0x07 // 'Status' register address
00114 #define OBSERVE_TX 0x08 // 'Observe TX' register address
00115 #define CD 0x09 // 'Carrier Detect' register address
00116 #define RX_ADDR_P0 0x0A // 'RX address pipe0' register address
00117 #define RX_ADDR_P1 0x0B // 'RX address pipe1' register address
00118 #define RX_ADDR_P2 0x0C // 'RX address pipe2' register address
00119 #define RX_ADDR_P3 0x0D // 'RX address pipe3' register address
00120 #define RX_ADDR_P4 0x0E // 'RX address pipe4' register address
00121 #define RX_ADDR_P5 0x0F // 'RX address pipe5' register address
00122 #define TX_ADDR 0x10 // 'TX address' register address
00123 #define RX_PW_P0 0x11 // 'RX payload width, pipe0' register address
00124 #define RX_PW_P1 0x12 // 'RX payload width, pipe1' register address
00125 #define RX_PW_P2 0x13 // 'RX payload width, pipe2' register address
00126 #define RX_PW_P3 0x14 // 'RX payload width, pipe3' register address
00127 #define RX_PW_P4 0x15 // 'RX payload width, pipe4' register address
00128 #define RX_PW_P5 0x16 // 'RX payload width, pipe5' register address
00129 #define FIFO_STATUS 0x17 // 'FIFO Status Register' register address
00130
00131
00132 #define NRF_RX_DR 6
00133 #define NRF_TX_DR 5
00134 #define NRF_MAX_RT 4
00135
00136
00137
00138
00139
00140 #define NFR_read_reg(reg) (NRF_Read(reg|READ_REG))
00141 #define NFR_write_reg(reg,val) (NRF_RW_Reg(reg|WRITE_REG,val))
00142
00143 #define NRF_init_tx() (NRF_disable(),NFR_write_reg(CONFIG,0x0A)) // Prim TX, CRC
00144 #define NRF_init_rx() (NRF_disable(),NFR_write_reg(CONFIG,0x0B),NRF_enable()) // Prim RX, CRC, PowerUp
00145
00146 #define Is_not_NRF_IRQ() ((NRF_IRQ_PORT & (1<<NRF_IRQ_PIN))? TRUE : FALSE)
00147 #define Is_NRF_IRQ() ((NRF_IRQ_PORT & (1<<NRF_IRQ_PIN))? FALSE : TRUE)
00148
00149
00150 #define NRF_tx_buffer(buf,n) (NRF_write_buf(WR_TX_PLOAD,buf,n))
00151 #define NRF_rx_buffer(buf,n) (NRF_read_buf(RD_RX_PLOAD,buf,n))
00152
00153 #define NRF_set_payload(pipe,n) (NFR_write_reg(RX_PW_P##pipe,n))
00154
00155 #define NRF_set_channel(n) (NFR_write_reg(RF_CH,n))
00156 #define NRF_set_byte_addr(n) (NFR_write_reg(SETUP_AW,n-2))
00157
00158 #define NRF_ack_RX_DR() (NFR_write_reg(STATUS,(1<<NRF_RX_DR)))
00159 #define NRF_ack_TX_DR() (NFR_write_reg(STATUS,(1<<NRF_TX_DR)))
00160 #define NRF_ack_MAX_RT() (NFR_write_reg(STATUS,(1<<NRF_MAX_RT)))
00161 #define NRF_ack_received() (NRF_ack_RX_DR())
00162 #define NRF_ack_transmit() (NRF_ack_TX_DR())
00163 #define NRF_ack_timeout() (NRF_ack_MAX_RT())
00164
00165 #define NRF_flush_rx() (NFR_write_reg(FLUSH_RX,0))
00166
00167 #define Is_NRF_RX_DR() (NFR_read_reg(STATUS)&(1<<NRF_RX_DR) ? TRUE : FALSE)
00168 #define Is_NRF_TX_DR() (NFR_read_reg(STATUS)&(1<<NRF_TX_DR) ? TRUE : FALSE)
00169 #define Is_NRF_MAX_RT() (NFR_read_reg(STATUS)&(1<<NRF_MAX_RT) ? TRUE : FALSE)
00170
00171 #define Is_NRF_received() (Is_NRF_RX_DR())
00172 #define Is_NRF_transmit() (Is_NRF_TX_DR())
00173 #define Is_NRF_timeout() (Is_NRF_MAX_RT())
00174
00175 #define NRF_Write_addr(reg,buf,n) NRF_write_buf(reg+0x20,buf, n)
00176
00177
00178
00179 U8 SPI_RW(U8 byte);
00180 U8 NRF_Read(U8 reg);
00181 U8 NRF_RW_Reg(U8 reg, U8 value);
00182 U8 NRF_read_buf(U8 reg, U8 *pBuf, U8 bytes);
00183 U8 NRF_write_buf(U8 reg, U8 *pBuf, U8 bytes);
00184
00185
00186
00187 #if 0
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00293 #endif