spi_drv.h

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00001 /*This file has been prepared for Doxygen automatic documentation generation.*/
00013 
00014 /* Copyright (c) 2007, Atmel Corporation All rights reserved.
00015  *
00016  * Redistribution and use in source and binary forms, with or without
00017  * modification, are permitted provided that the following conditions are met:
00018  *
00019  * 1. Redistributions of source code must retain the above copyright notice,
00020  * this list of conditions and the following disclaimer.
00021  *
00022  * 2. Redistributions in binary form must reproduce the above copyright notice,
00023  * this list of conditions and the following disclaimer in the documentation
00024  * and/or other materials provided with the distribution.
00025  *
00026  * 3. The name of ATMEL may not be used to endorse or promote products derived
00027  * from this software without specific prior written permission.
00028  *
00029  * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED
00030  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
00031  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND
00032  * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,
00033  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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00038  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00039  */
00040 
00041 #ifndef _SPI_DRV_H_
00042 #define _SPI_DRV_H_
00043 
00044 /*_____ I N C L U D E S  ___________________________*/
00045 
00046 #include "config.h"
00047 /*_____ M A C R O S  ___________________________*/
00048 
00049 /* SPI CONTROLLER */
00050 
00051 
00052 #define MSK_SPI_SPIE  0x80
00053 #define MSK_SPI_SPE   0x40
00054 #define MSK_SPI_DORD  0x20
00055 #define MSK_SPI_MSTR  0x10
00056 #define MSK_SPI_CPOL  0x08
00057 #define MSK_SPI_CPHA  0x04
00058 #define MSK_SPI_SPR1  0x02
00059 #define MSK_SPI_SPR0  0x01
00060 
00061 
00062 #define MSK_SPI_ENABLE_IT  0x80  
00063 #define MSK_SPI_ENABLE     0x40
00064 #define MSK_SPI_MASTER_MODE   0x10
00065 #define MSK_SPI_DOUBLESPEED   0x01
00066 
00067 #define MSK_SPI_DIV4          0x00
00068 #define MSK_SPI_DIV16         0x01
00069 #define MSK_SPI_DIV64         0x02
00070 #define MSK_SPI_DIV128        0x03
00071 #define MSK_SPI_CPHA_LEADING     0x00
00072 #define MSK_SPI_CPHA_TRAILING    0x04
00073 #define MSK_SPI_CPOL_HIGH     0x08
00074 #define MSK_SPI_CPOL_LOW      0x00
00075 #define MSK_SPI_LSBFIRST      0x20
00076 #define MSK_SPI_MSBFIRST      0x00
00077 #define MSK_SPI_CONF          0x2F
00078 #define MSK_SPI_SPIF          0x80
00079 #define MSK_SPI_MODE       0x0C
00080 #define MSK_MSTR                0x10
00081 
00082 /*----- Modes -----*/
00083 #define SPI_MASTER_MODE_0 (Byte)(MSK_MSTR)
00084 #define SPI_MASTER_MODE_1 (Byte)(MSK_MSTR|0x04)
00085 #define SPI_MASTER_MODE_2 (Byte)(MSK_MSTR|0x08)
00086 #define SPI_MASTER_MODE_3 (Byte)(MSK_MSTR|0x0C)
00087 
00088 #define SPI_SLAVE_MODE_0  (Byte)0x00
00089 #define SPI_SLAVE_MODE_1  (Byte)0x04
00090 #define SPI_SLAVE_MODE_2  (Byte)0x08
00091 #define SPI_SLAVE_MODE_3  (Byte)0x0C
00092 
00093 /*----- Bit rates -----*/
00094 //#define SPI_RATE_0        (Byte)0x00    /* Fper / 2 */
00095 #define SPI_RATE_1        (Byte)0x00    /* Fper / 4 */
00096 //#define SPI_RATE_2        (Byte)0x02    /* Fper / 8 */
00097 #define SPI_RATE_3        (Byte)0x01    /* Fper / 16 */
00098 //#define SPI_RATE_4        (Byte)0x80    /* Fper / 32 */
00099 #define SPI_RATE_5        (Byte)0x02    /* Fper / 64 */
00100 #define SPI_RATE_6        (Byte)0x03    /* Fper / 128 */
00101 
00102 /*______  D E F I N I T I O N  ___________________________*/
00103 
00104 
00105 #define Spi_enable()            (SPCR |=MSK_SPI_ENABLE)
00106 #define Spi_disable()           (SPCR &= ~MSK_SPI_ENABLE)
00107 #define Spi_enable_it()         (SPCR|= MSK_SPI_ENABLE_IT)
00108 #define Spi_disable_it()        (SPCR&=~MSK_SPI_ENABLE_IT)
00109 #define Spi_select_slave_mode() (SPCR&=~MSK_SPI_MASTER_MODE)
00110 #define Spi_select_master_mode() (SPCR|= MSK_SPI_MASTER_MODE)
00111 #define Spi_set_mode(mode)      (SPCR &= ~(MSK_SPI_MASTER_MODE|MSK_SPI_MODE )); (SPCR |= mode);Spi_init_bus()
00112 #define Spi_read_data()         (SPDR)
00113 #define Spi_get_byte()          (SPDR)
00114 #define Spi_write_data(ch)      (SPDR=ch);Spi_wait_spif();
00115 #define Spi_send_byte(ch)       (SPDR=ch);Spi_wait_spif();
00116 #define Spi_wait_spif()         while ((SPSR & MSK_SPI_SPIF) == 0) /* for any SPI_RATE_x */
00117 #define Spi_wait_eor()          while ((SPSR & MSK_SPI_SPIF) == 0) /* wait end of reception */
00118 #define Spi_wait_eot()          while ((SPSR & MSK_SPI_SPIF) == 0) /* wait end of transmission */
00119 #define Spi_eor()               ((SPSR & MSK_SPI_SPIF) == MSK_SPI_SPIF)/* check end of reception */
00120 #define Spi_eot()               ((SPSR & MSK_SPI_SPIF) == MSK_SPI_SPIF)/* check end of transmission */
00121 #define Spi_set_doublespeed()   (SPSR|= MSK_SPI_DOUBLESPEED)
00122 #define Spi_hw_init(conf)       (SPCR&=~MSK_SPI_CONF, SPCR|=conf)
00123 #define Spi_get_colision_status() (SPSR&(1<<WCOL))
00124 #define Spi_get_byte()          (SPDR)
00125 #define Spi_tx_ready()          (SPSR & (1<<SPIF))
00126 #define Spi_rx_ready()            Spi_tx_ready()
00127 #define Spi_init_bus()           ((DDRB |= (1<<DDB2)|(1<<DDB1)))
00128 #define Spi_disable_ss()
00129 #define Spi_enble_ss()
00130 
00131 #define Spi_write_dummy()       (SPDR = 0x00);Spi_wait_spif();
00132 #define Spi_read_dummy()        (0x00 = SPDR)
00133 #define Spi_config_speed(config) (SPCR &= ~(MSK_SPI_SPR1|MSK_SPI_SPR0), (SPCR |= config))/*see bit rates for config*/
00134 //#define Spi_set_rate(rate)      (SPCR &= ~MSK_SPR); (SPCR |= rate);(if (rate == (SPI_RATE_0|SPI_RATE_2|SPI_RATE_4) doublespeed());
00135 
00136 #ifndef DUMMY
00137   #error "DUMMY should be define in config.h as free general purpose IO register"
00138 #endif
00139 #define Spi_ack_read()          (DUMMY = SPSR)
00140 #define Spi_ack_write()         (DUMMY = SPDR)
00141 #define Spi_ack_cmd()           (DUMMY = SPSR)
00142 
00143 
00144 #endif  /* _SPI_DRV_H_ */
00145 

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