power_drv.h

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00001 /*This file has been prepared for Doxygen automatic documentation generation.*/
00016 
00017 /* Copyright (c) 2007, Atmel Corporation All rights reserved.
00018  *
00019  * Redistribution and use in source and binary forms, with or without
00020  * modification, are permitted provided that the following conditions are met:
00021  *
00022  * 1. Redistributions of source code must retain the above copyright notice,
00023  * this list of conditions and the following disclaimer.
00024  *
00025  * 2. Redistributions in binary form must reproduce the above copyright notice,
00026  * this list of conditions and the following disclaimer in the documentation
00027  * and/or other materials provided with the distribution.
00028  *
00029  * 3. The name of ATMEL may not be used to endorse or promote products derived
00030  * from this software without specific prior written permission.
00031  *
00032  * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED
00033  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
00034  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND
00035  * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,
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00037  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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00043 
00044 
00045 #ifndef _POWER_DRV_H_
00046 #define _POWER_DRV_H_
00047 
00048 #ifdef __GNUC__
00049 #ifndef CLKSEL0 
00050    #define CLKSEL0  _SFR_MEM8(0XD0)
00051 #endif
00052 #ifndef CLKSEL1 
00053    #define CLKSEL1  _SFR_MEM8(0XD1)
00054 #endif
00055 #ifndef CLKSTA 
00056    #define CLKSTA   _SFR_MEM8(0XD2)
00057 #endif
00058 #endif
00059 
00063 
00064 //_____ M A C R O S ________________________________________________________
00065 
00066 #define Setup_idle_mode()                (SMCR=0,SMCR |= (1<<SE))
00067 #define Setup_power_down_mode()                   (SMCR=0,SMCR |= (1<<SE)+(1<<SM1))
00068 #define Setup_adc_noise_reduction_mode()          (SMCR=0,SMCR |= (1<<SE)+(1<<SM0))
00069 #define Setup_power_save_mode()                          (SMCR=0,SMCR |= (1<<SE)+(1<<SM1)+(1<<SM0))
00070 #define Setup_standby_mode()                     (SMCR=0,SMCR |= (1<<SE)+(1<<SM2)+(1<<SM1))
00071 #define Setup_ext_standby_mode()                  (SMCR=0,SMCR |= (1<<SE)+(1<<SM2)+(1<<SM1)+(1<<SM0))
00072 
00082 #define Clear_prescaler()                       (CLKPR = (1<<CLKPCE),CLKPR = 0)
00083 
00093 #define Set_prescaler(x)                        (CLKPR = (1<<CKLPCE),CLKPR = x)
00094 
00095 
00096 #define Sleep_instruction()              {asm("SLEEP");}
00097 
00098 //Backward compatibility
00099 #define Set_power_down_mode()              set_power_down_mode()
00100 #define Set_idle_mode()          set_idle_mode()
00101 
00102 //_____ D E C L A R A T I O N ______________________________________________
00103 
00104 void set_idle_mode(void);
00105 void set_power_down_mode(void);
00106 void set_adc_noise_reduction_mode(void);
00107 void set_power_save_mode(void);
00108 void set_standby_mode(void);
00109 void set_ext_standby_mode(void);
00110 
00119 #define Enter_idle_mode()                 (set_idle_mode())
00120 
00129 #define Enter_power_down_mode()           (set_power_down_mode())
00130 
00139 #define Enter_adc_noise_reduction_mode()  (set_adc_noise_reduction_mode())
00140 
00149 #define Enter_power_save_mode()           (set_power_save_mode())
00150 
00159 #define Enter_standby_mode()              (set_standby_mode())
00160 
00169 #define Enter_ext_standby_mode()          (set_ext_standby_mode())
00170 
00171 
00173 
00174 
00175 
00176 
00180 
00181 //_____ M A C R O S ________________________________________________________
00182 
00183 // Clock control
00184 #define   Enable_external_clock()       (CLKSEL0 |= (1<<EXTE))
00185 #define   Disable_external_clock()      (CLKSEL0 &= ~(1<<EXTE))
00186 #define   Enable_RC_clock()             (CLKSEL0 |= (1<<RCE))
00187 #define   Disable_RC_clock()            (CLKSEL0 &= ~(1<<RCE))
00188 
00189 // Clock state
00190 #define   External_clock_ready()        (((CLKSTA&(1<<EXTON)) != 0) ? TRUE : FALSE)
00191 #define   RC_clock_ready()              (((CLKSTA&(1<<RCON)) != 0) ? TRUE : FALSE)
00192 
00193 // Clock selection
00194 #define   Select_external_clock()       (CLKSEL0 |= (1<<CLKS))
00195 #define   Select_RC_clock()             (CLKSEL0 &= ~(1<<CLKS))
00196 
00197 // Clock settings : when using a clock source, only the other clock source setting can be modified
00198 // Set the source setting of the next clock source to use before switching to it
00199 #define   Load_ext_clock_config(cfg)    (CLKSEL1 = (CLKSEL1&0xF0) | ((cfg&0x0F)<<EXCKSEL0), \
00200                                          CLKSEL0 = (CLKSEL0&0xCF) | (((cfg&0x30)>>4)<<EXSUT0))
00201 
00202 #define   Load_RC_clock_config(cfg)     (CLKSEL1 = (CLKSEL1&0x0F) | ((cfg&0x0F)<<RCCKSEL0), \
00203                                          CLKSEL0 = (CLKSEL0&0x3F) | (((cfg&0x30)>>4)<<RCSUT0))
00204 
00205 //_____ C L O C K   D E F I N I T I O N S ______________________________________
00206 // Configuration byte defined as SUT<1:0> & CKSEL<3:0> (CKSEL0 is the LSb)
00207 
00208 // Interal RC oscillator (frequency between 7.3 and 8.1 MHz)
00209 #define   OSC_INTRC_0MS                  0x02
00210 #define   OSC_INTRC_4MS                  0x12
00211 #define   OSC_INTRC_65MS                 0x22
00212 
00213 // External crystal, frequency between 0.3 and 0.9 MHz
00214 #define   OSC_XTAL_RANGE1_258CK_4MS      0x08
00215 #define   OSC_XTAL_RANGE1_258CK_65MS     0x18
00216 #define   OSC_XTAL_RANGE1_1KCK_0MS       0x28
00217 #define   OSC_XTAL_RANGE1_1KCK_4MS       0x38
00218 #define   OSC_XTAL_RANGE1_1KCK_65MS      0x09
00219 #define   OSC_XTAL_RANGE1_16KCK_0MS      0x19
00220 #define   OSC_XTAL_RANGE1_16KCK_4MS      0x29
00221 #define   OSC_XTAL_RANGE1_16KCK_65MS     0x39
00222 
00223 // External crystal, frequency between 0.9 and 3 MHz
00224 #define   OSC_XTAL_RANGE2_258CK_4MS      0x0A
00225 #define   OSC_XTAL_RANGE2_258CK_65MS     0x1A
00226 #define   OSC_XTAL_RANGE2_1KCK_0MS       0x2A
00227 #define   OSC_XTAL_RANGE2_1KCK_4MS       0x3A
00228 #define   OSC_XTAL_RANGE2_1KCK_65MS      0x0B
00229 #define   OSC_XTAL_RANGE2_16KCK_0MS      0x1B
00230 #define   OSC_XTAL_RANGE2_16KCK_4MS      0x2B
00231 #define   OSC_XTAL_RANGE2_16KCK_65MS     0x3B
00232 
00233 // External crystal, frequency between 3 and 8 MHz
00234 #define   OSC_XTAL_RANGE3_258CK_4MS      0x0C
00235 #define   OSC_XTAL_RANGE3_258CK_65MS     0x1C
00236 #define   OSC_XTAL_RANGE3_1KCK_0MS       0x2C
00237 #define   OSC_XTAL_RANGE3_1KCK_4MS       0x3C
00238 #define   OSC_XTAL_RANGE3_1KCK_65MS      0x0D
00239 #define   OSC_XTAL_RANGE3_16KCK_0MS      0x1D
00240 #define   OSC_XTAL_RANGE3_16KCK_4MS      0x2D
00241 #define   OSC_XTAL_RANGE3_16KCK_65MS     0x3D
00242 
00243 // External crystal, frequency between 8 and 16 MHz
00244 #define   OSC_XTAL_RANGE4_258CK_4MS      0x0E
00245 #define   OSC_XTAL_RANGE4_258CK_65MS     0x1E
00246 #define   OSC_XTAL_RANGE4_1KCK_0MS       0x2E
00247 #define   OSC_XTAL_RANGE4_1KCK_4MS       0x3E
00248 #define   OSC_XTAL_RANGE4_1KCK_65MS      0x0F
00249 #define   OSC_XTAL_RANGE4_16KCK_0MS      0x1F
00250 #define   OSC_XTAL_RANGE4_16KCK_4MS      0x2F
00251 #define   OSC_XTAL_RANGE4_16KCK_65MS     0x3F
00252 
00253 // External clock
00254 #define   OSC_EXTCLK_0MS                 0x00
00255 #define   OSC_EXTCLK_4MS                 0x10
00256 #define   OSC_EXTCLK_65MS                0x20
00257 
00258 
00259 //_____ D E C L A R A T I O N ______________________________________________
00260 
00261 void Clock_switch_external(void);
00262 void Clock_switch_internal(void);
00263 
00265 
00266 
00267 #endif  // _POWER_DRV_H_
00268 

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